The invention relates to a method for fabricating a semiconductor structure having selective dopant regions.
Semiconductor technologies for applications appertaining to automotive, industrial and consumer electronics are distinguished by a multiplicity of semiconductor components for realizing different types of circuit blocks such as, for instance, analog, digital or power circuit blocks and are known as BCD, SPT or else SMART technology.
Some of these semiconductor technologies have only a single polysilicon layer having a specific layer conductivity for realizing components, in order not to drive up the costs of a mask set through additional masks for patterning further polysilicon layers. A polysilicon layer serves for example for forming gate electrode structures, capacitance electrode structures or else diode structures.
A technology with a single polysilicon layer having a specific conductivity entails the disadvantage, however, that it is not possible to form diodes insulated from the substrate and made from polysilicon. However, diodes of this type enable extensive advantages, for instance with regard to the design of charge pumps. With a single polysilicon layer having a specific conductivity it is likewise not possible to realize a broader range of resistances, e.g., resistances insulated from the substrate and made from polysilicon on a small area. However, flexibility with regard to the value of the conductivity and the conductivity type of polysilicon enables further advantages with regard to the match behavior of the threshold voltages of NMOS (n-type metal oxide semiconductor) and PMOS (p-type metal oxide semiconductor) field effect transistors without additional implantations (e.g., channel implantation). An implantation of dopants through a gate electrode structure right into a channel region of a planar MOSFET could likewise be avoided.
For these and other reasons, there is a need for the present invention.